This invention pertains to a type of timer circuit. More specifically, this invention pertains to a technology that provides a type of timer circuit with low power consumption and an output signal having a very stable frequency.
In a silicon IC, etc., an on-chip timer circuit is provided.
FIG. 2 is a diagram illustrating timer circuit 101 as an example. This timer circuit 101 has crystal oscillator 111 and frequency divider 112. The signal generated by crystal oscillator 111 is subject to frequency division by frequency divider 112, and an output signal at a prescribed frequency is output to an external circuit not shown in the figure.
For said timer circuit 101, because crystal oscillator 111 with a stable oscillation frequency is used, frequency of the output signal is stable. However, crystal oscillator 111 has a high power consumption. Consequently, it is inappropriate for use in a timer circuit with a power consumption level of about 0.1 xcexcW.
In order to solve this problem, it has been proposed that a ring oscillator of lower power consumption be used. For example, when a ring oscillator composed of a CMOS or other low-power elements is used as the oscillator, it is quite possible to form a timer circuit with a power consumption as low as about 0.1 xcexcW.
However, although a ring oscillator has low power consumption, its oscillation frequency is unstable due to variation in temperature and variations in manufacturing processing. Consequently, it is hard for it to realize the function of a timer circuit.
An object of this invention is to solve the problems of conventional methods by providing a type of timer circuit which has low power consumption and high stability for the frequency of the output signal.
In accordance with one aspect of this invention a timer circuit has a first oscillator that outputs a first oscillation signal, a second oscillator that outputs a second oscillation signal at high precision, a frequency divider that performs frequency division for the first oscillation signal at a prescribed frequency dividing value and outputs an output signal at a prescribed frequency, a frequency dividing value setting circuit that sets the frequency dividing value of the frequency divider based on the first oscillation signal and the second oscillation signal, and a controller that controls the operation of the second oscillator and the frequency dividing value setting circuit such that the second oscillator and the frequency dividing value setting circuit work intermittently; in this timer circuit, under control of the controller, the second oscillator and the frequency dividing value setting circuit work intermittently, and the frequency of the output signal output from the frequency divider is controlled to be constant.
In accordance with an aspect of the invention, it is preferred that the frequency dividing value setting circuit have an arithmetic operation circuit that determines the frequency ratio of the first oscillation signal to the second oscillation signal, a memory circuit that stores a prescribed value, and a frequency dividing value controller that determines the frequency dividing value of the frequency divider corresponding to the frequency ratio and the prescribed value.
In addition, it is preferred that the first oscillator be a ring oscillator, and the second oscillator be a crystal oscillator.
Furthermore, it is preferred that the timer circuit have a battery for feeding electric power to the first oscillator, the second oscillator, the frequency divider, the frequency dividing value setting circuit, and the controller, and the first oscillator, the second oscillator, the frequency divider, the frequency dividing value setting circuit, the controller, and the battery be formed as a single body by molding.
According to a further aspect of this invention the timer circuit has a second oscillator as a highly stable oscillator, an arithmetic operation circuit, and a frequency dividing value controller. The highly stable oscillator generates a second oscillation signal as a standard signal. The arithmetic operation circuit determines the frequency ratio of the frequency of the first oscillation signal, which is an internal signal, and the frequency of the standard signal. The frequency dividing value controller changes the frequency dividing value of the frequency divider corresponding to the frequency ratio. For example, the frequency ratio in the state when the frequency of the output signal is in agreement with a prescribed target frequency is stored. By comparing the actually measured frequency ratio and the stored frequency ratio, it is possible to know the degree of difference between the frequency of the internal signal and the frequency of the standard signal. As a result, even when the frequency of the internal signal varies, by setting an appropriate frequency dividing value corresponding to the variation, it is possible to maintain the frequency of the output signal at a prescribed frequency with high stability without variation.
Also, in accordance with an aspect of this invention a controller (wake-up circuit) controls so that at least the highly stable oscillator works intermittently. Thus, even when the highly stable oscillator is a crystal oscillator or another device that has a high power consumption, because the operation time of the highly stable oscillator with respect to the entire operation time of the timer circuit is short, power consumption by the highly stable oscillator is lower than that if it worked all the time. As a result, the overall power consumption of the timer circuit can be lowered.